1. Field of the Invention
The present invention relates to fabricating a via employed in an integrated circuit that is substantially free of metal polymer and oxide polymer residues. More particularly, the present invention relates to a two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures carried on a semiconductor substrate.
2. State of the Art
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. One commonly used technique in the fabrication of integrated circuits involves stacking of multiple layers of active and passive components one atop another to allow for multilevel electrical interconnection between devices formed on each of these layers. This multilevel electrical interconnection is generally achieved with a plurality of metal-filled vias (“contacts”) extending through dielectric layers that separate the component layers from one another. These vias are generally formed by anisotropically etching through each dielectric layer by etching methods known in the industry, such as plasma etching and reactive ion etching. A fluorinated gas, such as CF4, CHF3, C2F6, CH2F2, SF6, or other freons, and mixtures thereof, in combination with a carrier gas, such as Ar, He, Ne, Kr, O2, or mixtures thereof, is usually used as the etching gas for these etching methods. A problem with such etching methods is that at least one layer of residue forms in the vias as a result of the etching process.
An exemplary method for forming a via through a dielectric layer is illustrated in FIGS. 11-14. It should be understood that the figures presented in conjunction with this description are not meant to be actual cross-sectional views of any particular portion of an actual semiconductor device, but are merely idealized representations that are employed to more clearly and fully depict the process of this typical method than would otherwise be possible.
FIG. 11 illustrates an intermediate structure 200 comprising a semiconductor substrate bearing a dielectric or insulating layer 202 (such as an oxide) having a metal-containing trace or pad 204 of aluminum, aluminum alloys, titanium, titanium/tungsten alloys, molybdenum, or the like, formed thereon. The term “semiconductor substrate” is used herein to denote any solid semiconductor surface, such as is provided by a silicon or gallium arsenide wafer, or a layer of such material formed on glass, ceramic, sapphire, or other supporting carrier, as known in the art, and includes such semiconductor surfaces bearing an insulating layer thereon. A barrier layer 206 (such as titanium nitride) extends over the metal-containing trace or pad 204, and an interlayer dielectric 208 (such as silicon dioxide) is disposed over the barrier layer 206. As shown in FIG. 12, the interlayer dielectric 208 is masked with a resist material 212, which is then patterned to define a via location. A partial via 214 is then selectively etched with a fluorinated gas down to the barrier layer 206, which acts as an etch stop. The etching of the partial via 214 results in a first residue layer 216 of a carbon-fluorine based, polymer-containing residue of the interlayer dielectric 208 (“oxide polymer”) coating the sidewall 218 of the partial via 214, as shown in FIG. 13. The barrier layer 206 at the bottom of partial via 214 is then etched to expose the metal-containing trace or pad 204 and form a full via 222, as shown in FIG. 14. However, due to the variation in the thickness of the interlayer dielectric 208 from the center of the wafer to the edge (usually between 4000 and 5000 Å), an oxide over-etch is applied, such that the via will usually extend through the barrier layer 206 and into the metal-containing trace or pad 204. When the barrier layer 206 and metal-containing trace or pad 204 are etched, a second residue layer 224 (“metal polymer”) of a carbon-fluorine based polymer including metal etched from the metal-containing trace or pad 204, as well as any metal components in the barrier layer 206, such as the titanium in a titanium nitride barrier layer, is formed over the first residue layer 216 and the exposed surface 226 of the metal-containing trace or pad 204, also shown in FIG. 14. It is, of course, understood that a single etch could be performed to expose the metal-containing trace or pad 204, which etch would result in a single residue layer. However, even if a single etch were performed, the single residue layer would still have a portion of the residue layer adjacent the via sidewall 218 containing primarily oxide polymer and a portion adjacent the via aperture and the bottom of the via containing primarily metal polymer.
Residue layers, such as first residue layer 216 and second residue layer 224, which coat the full via 222, are very difficult to remove. These residue layers may be removed by dipping the structure in a 35° C. phosphoric acid solution, preferably about a 20:1 ratio (volume of water to volume of acid) solution, for about 90 seconds. Although this technique is effective in removing most of the residue layers, the residue layers are still not completely removed. The portion of the residue still remaining after the phosphoric acid dip adversely affects the conductivity of contacts subsequently formed in the full via 222. It is noted that, although extending the residence time of the semiconductor substrate structure in the phosphoric acid will effectively remove all of the residue layer(s), the increased residence time also results in damage to the metal-containing trace or pad 204.
Thus, it can be appreciated that it would be advantageous to develop a technique to clean substantially all ofthe residue layer(s) from a semiconductor via without substantial damage to the metal-containing trace or pad while using commercially available, widely practiced semiconductor device fabrication techniques.